1. Field of Invention
This invention relates to analog-to-digital converters. Specifically, the present invention relates to high resolution, monolithic, high speed analog-to-digital converters.
2. Description of the Related Art
Analog to digital converters (ADCs) are well known in the art. These devices convert analog signals to digital signals and are therefore used in a variety of applications. Several ADC techniques are known in the art.
A switched-capacitor ADC uses a CMOS comparator in a successive approximation system to determine each bit by examining the charge on a series of binary-weighted capacitors. In the first phase of the conversion process, the analog input is sampled by closing switches simultaneously charge a plurality of capacitors in parallel interconnection to the input analog voltage. In the next phase of the conversion process, all switches are opened and the comparator begins identifying bits by identifying the charge on each capacitor relative to the reference volts. In the switching sequence, all capacitors are examined separately until all bits are identified, and then the charge-convert sequence is repeated. In the first step of the conversion phase, the comparator looks at the first capacitor having a binary weight of 128. One pole of the capacitor is switched to the reference voltage, and the equivalent poles of all the other capacitors on the ladder are switched to ground. If the voltage at the summing node is greater than the trip point of the comparator, approximately xc2xd the reference voltage, a bit is placed in the output register, and the 128 weight capacitor is switched to ground. If the voltage at the summing node is less than the trip point of the comparator, this 128 weight capacitor remains connected to the reference input through the remainder of the capacitor sampling process. The process is repeated for the 64-weight capacitor, the 32-weight capacitor and so forth until all bits are tested. With each step of the capacitor sampling process, the initial charge is redistributed among the capacitors. The conversion process is successive approximation, but relies on charge shifting rather than a successive approximation register and a reference digital to analog converter (D/A or DAC) to count and weigh the bits from the MSB to the LSB.
In a tracking ADC an analog input is fed into a span resistor of a DAC. The analog input voltage range is selectable in the same way as the output voltage range of the DAC. The net current flow through a ladder termination resistance produces an error voltage at the DAC output. This error voltage is compared with xc2xd LSB by a comparator. When the error voltage is within +/xe2x88x92xc2xd LSB range, the output of + to xe2x88x92 common comparators are both low, which stops the counter and gives a data ready signal to indicate that the digital output is correct. If the error exceeds the +/xe2x88x92LSB range, the counter is enabled and driven in an up or down direction depending on the polarity of the error voltage. The digital output changes state only when there is a significant change in the analog input. When monitoring a slowly varying input, it is necessary to read the digital output only after a change has taken place. The data ready signal could be used to trigger a flip-flop to indicate the condition and reset it after readout. The main disadvantage of the tracking ADC is the time required to initially acquire a signal; for a 12 bit ADC, it could be up to 4096 clock periods. The input signal usually must be filtered so that its rate of change does not exceed the tracking range of the ADC, i.e., 1 LSB per clock period.
An A/D conversion technique which combines some of the speed advantages of flash conversion with the circuitry savings of successive approximation is termed xe2x80x9chalf-flashxe2x80x9d or subranging ADC. In an 8 bit, half-flash converter, two 4 bit flash A/D sections are combined. The upper flash A/D compares the input signal to the reference and generates the upper 4 data bits. This data goes to an internal DAC, whose output is subtracted from the analog input. Then, the difference is measured by the second flash A/D, which provides the lower 4 data bits.
Of particular relevance is a technical paper by Todd L. Brooks, et al of Analog Devices, Inc., Wilmington, Mass., and presented at the IEEE International Solid-State Circuits Conference in 1997 and also a U.S. Pat. No. 5,936,562 to Brooks, et al issued on Aug. 10, 1999, the teachings of which are incorporated herein by reference. Brooks, et al describe a 16 bit sigma-delta (SD) pipeline ADC with 2.5 MHz output data rate. This device is fabricated in 0.6 um CMOS and addresses the need for a wide dynamic range ADC with bandwidth in excess of 1 MHz in multi-tone communication. This ADC combines the advantages of SD and pipeline ADC techniques to provide wide dynamic range with a low-oversampling ratio. The device operates at a 20 MHz clock rate, 2.5 MHz output rate (8xc3x97 oversampling), and provides 89 dB SNR over a 1.23 MHz input bandwidth. This is a two-pass subranging architecture, where the fine encoder is a subranging 12 bit ADC that is oversampled by 8xc3x97, and the coarse encoder is a 5 bit SD. The process used is CMOS and the DAC is a switched capacitor circuit with randomization to improve the integral nonlinearity of the DAC.
However, this approach has many problems. The differential nonlinearity (DNL) of this DAC is limited by the achievable capacitor matching of the CMOS process. Randomization helps the spur free dynamic range, see FIGS. 5 and 6 of the reference, but only at the expense of signal-to-noise ratio (SNR) degradation. Also, as is well known, CMOS technology limits dynamic range.
Another disadvantage of this device is that it requires 8xc3x97 higher clock rate although the bandwidth is on {fraction (1/16)} of that clock rate and the clock signal must be inserted into the integrated circuit (IC).
Hence, a need remains in the art for an improved analog to digital converter design.
The need in the art is addressed by the analog to digital converter architecture of the present invention. The invention is a high performance ADC apparatus comprising a front end ADC baseline device providing a baseline bit size at a baseline data rate and having a selected dynamic range at a baseline clock rate. A second circuit decimates the baseline data rate of the baseline device to a data rate reduced by the selected factor, so as to achieve an oversampling rate equal to the selected factor. Finally, a circuit is employed for producing an output data rate less than the baseline clock rate by the selected factor with a final, high resolution.
In the illustrative implementation, the baseline clock rate is generated, by multiplying the crystal oscillator reference frequency, by a selected factor, through the use of a PLL. The reference clock frequency is the clock rate of the final, high resolution ADC.